Kibra 480 Analyzer

Kibra 480 Analyzer

The Kibra 480 is a stand-alone protocol analyzer that provides comprehensive bus and JEDEC timing analysis for DDR3 and DDR4. Sitting in-line on a live system, the analyzer uses a proprietary probe implementation to allow loss-less capture of high speed DDR transactions while automatically identifying timing and protocol violations.

The Teledyne LeCroy Kibra 480 is a stand-alone protocol analyzer that provides comprehensive DDR3 and DDR4 JEDEC timing analysis. Based on the ground breaking Kibra 380, the 480 platform features proprietary probing technology designed to non-intrusively monitor higher speed DDR3 as well as the new DDR4 signaling. Sitting in-line on a live system, the analyzer records memory I/O while automatically identifying timing and protocol violations. It displays both commands and errors using a full function waveform viewer allowing fast debug of memory devices and controllers.

Teledyne LeCroy developed a custom ASIC for the Kibra 480 probe to support higher speed DDR memory. This proprietary probe implementation allows loss-less capture of DDR3 to 2133 MT/s; and DDR4 to 2400 MT/s. The probes are self-powered to allow instant signal lock – including reliable capture of the DDR4 power-on sequence. Separate probes are available for DDR3 and DDR4 supporting both U-DIMM/R-DIMM as well as SO-DIMM form-factors.

  • Fast and Easy Debug for DDR3 and DDR4
    • Self-contained system offers easy connection and setup
    • Custom probe design supports next generation higher speed memory
    • No calibration needed!
    • Free trace viewer runs on any PC
  • Comprehensive JEDEC Trigger and Capture
    • Detects over 65 JEDEC bus event & timing violations in real time
    • Extended recording time captures 4X the memory events vs. typical Logic Analyzer State listing
    • Interposers will snoop the serial presence detect (SPD) data for fast configuration of the analyzer
    • Dedicated trigger output to scope for Read/ Write operations
  • Innovative Displays Focused on Timing Analysis
    • Traditional State and Timing Waveform views
    • Visualize I/O distribution with the Bank State View
    • Bus metrics are tracked per bank and per DIMM slot
    • RTS view displays Bus Utilization in Real Time
    • Use "Row Hammer" reports to find excessive row ACTIVE commands
  • Flexible, Scalable Platform
    • Monitor two slots of quad rank DDR3 or DDR4 DIMMS concurrently
    • Supports registered buffered and unbuffered DIMM types
    • Address multi-channel application by cascading analyzers

Designed specifically to overcome the cost and complexity of monolithic test approaches that rely on logic analyzer platforms, the Kibra 480 is a fully self-contained solution offering easy connection to the system under test. Using "slot interposer" style probing, the analyzer transparently monitors the link to identify over 65 JEDEC state and timing violations in real time. The tester captures address, command and control signals (ADD/CMD/CNTRL). By focusing on state-based capture and excluding the data signals, the Kibra 480 allows quick analysis of memory transactions without the time consuming calibration and setup.

The Kibra 480 can specify custom triggers for any DDR command including MRS or Read/Write commands to a specific physical address. With the sequential triggering, the analyzer can wait for any command/control events in sequence including any combination of high/low signaling. Optionally add a timer within a sequence to specify a timeout condition or re-arm the analyzer. Filtering of NOP & Deselect commands is available to selectively capture the most important operations.

The Teledyne LeCroy system also features unique, real-time trigger-out to a scope for Read / Write operations (WE). Using this dedicated, low latency SMA trigger out signal, the scope can use the DQ/DQS relationships to distinguish between Read and Write operations on the bus.

In addition to timing analysis, the Kibra 480 generates performance metrics that are displayed for read, write, self-refresh, and power down operations. Bus metrics are tracked per bank, per rank and per bank group to provide insights into overall memory utilization.

Start using the Teledyne LeCroy Kibra 480 immediately without time consuming calibration. Simply enter the memory controller parameters and start recording. The software will automatically load JEDEC timing values for the DIMM type specified. Selectively enable, disable, or customize any of the JEDEC trigger values on-the-fly. When the analyzer detects a violation, markers are placed at each error event within the Timing view to make it easy to see and verify the JEDEC timing intervals.

The latest enhancements for the Kibra 480 include the ability to Follow MRS commands on-the-fly. Enabling this option allows the Kibra system to adjust the JEDEC timing intervals in real time. In the event the memory controller sends MRS commands that change specific parameters, this prevents the Kibra from detecting false errors (ie: MRS commands that change the burst length).

The new Row Usage report allows users to track the number of ACTIVATE commands sent to each row within a refresh cycle. Specifically designed to identify “Row Hammer” problems, it runs as a post-process to scan the trace and show any rows where excessive ACTIVATES may effect data integrity in the array. The new System Memory Map allows users to automatically translate the DRAM physical address into the logical System memory location. This allows improved correlation between processor, memory and expansion busses, such as PCI Express.

The Real Time Statistics (RTS) display tracks bus utilization and timing violations over extended periods. The RTS view shows each rank as a separate graph and can be paused, scrolled or saved to .CSV format.

Flexibility remains a hallmark of Teledyne LeCroy’s bus analyzer solutions. As an added convenience, the Kibra 480 can capture the serial presence detect (SPD) data from the bus allowing users to automatically discover and configure the memory parameters used by the system-under-test. Free downloadable software is available for sharing trace files within a development team. With its unprecedented ease of use and support for testing both DDR3 and DDR4, the Kibra 480 system allows SoC designers to leverage their R&D budgets and increase their test coverage of next generation DDR memory technology.