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QPHY-DDR4

QPHY-DDR4

DDR4 is an evolutionary upgrade from DDR3. It introduces data transfer rates which are nearly double the DDR3 transfer rates, ranging from 1.6 GT/s up to 3.2 GT/s. DDR4's higher transfer rates and lower operating voltage have driven new test methodologies and test requirements which were not previously required for DDR3 in order to ensure proper signal fidelity. QPHY-DDR4 has a full suite of Clock, Electrical, and Timing tests as specified by the JEDEC Specification which will aid in DDR4 design validation.

QPHY-BroadR-Reach Automotive Ethernet enables faster data communication to meet the demands of today’s vehicles and the connected vehicles of the future. QPHY-BroadR-Reach automates testing and validation of 100 Mb/s Automotive Ethernet, which is described in both the BroadR-Reach and 100Base-T1 (IEEE 802.3bw) specifications.
DDR Debug Toolkit The DDR Debug Toolkit provides test, debug and analysis tools for the entire DDR design cycle. The unique DDR analysis capabilities provide automatic Read and Write burst separation, bursted data jitter analysis and DDR-specific measurement parameters.
ET-PMT Electrical Telecom Mask Test Package
GRL-USB-PD GRL-USB-PD software provides a simple and efficient way to perform USB-PD electrical parametric and protocol measurements. GRL-USB-PD provides waveform visibility and protocol analysis making it ideal for design and debug of USB Type-C Power Delivery silicon and end products.
GRL-USB-PD-C1 GRL-USB-PD-C1 is a flexible test controller, designed for USB-PD Compliance testing of the Unit Under Test (UUT) and more.
LNES Low Noise Edge Shaper
QPHY-10GBase-KR The Teledyne LeCroy QPHY-10GBase-KR solution automates testing for 10Gigabite Ethernet Copper Backplane base on the IEEE 802.3ap specifications. The test framework simplifies the test setup and execution of generic and common test requirements such as jitter separation, rise/fall time and transmitter equalization parameters. The guided wizard prompts the user to for specification required patterns and takes the measurements accordingly. The test report includes the test results pass/fail summary, margins and limits, as well as waveforms and measurements used during the test process.
QPHY-10GBASE-T QPHY-10GBASE-T automated compliance test software performs electrical compliance testing of the Physical Media Attachment (PMA) for 10GBASE-T Ethernet PHY, based on IEEE802.3-2008 requirements.
QPHY-DDR2 The Teledyne LeCroy QPHY-DDR2 Test Solution is the best way to characterize DDR2 memory interfaces. Capable of performing measurements on 400 MHz, 533 MHz, 667 MHz, 800 MHz, 1066 MHz and custom speed grades, QPHY-DDR2 has a full suite of Clock, Electrical and Timing tests as specified by the JEDEC Specification and Intel JEDEC Specifications Addendums.
QPHY-DDR3 The Teledyne LeCroy QPHY-DDR3 Test Solution is the best way to characterize DDR3, DDR3L, and LPDDR3 memory interfaces. Capable of performing measurements on 800 MT/s, 1066 MT/s, 1333 MT/s, 1600 MT/s, 1866 MT/s, 2133 MT/s and custom speed grades, QPHY-DDR3 has a full suite of Clock, Electrical, and Timing tests as specified by the JEDEC Specification.
QPHY-DDR4 DDR4 is an evolutionary upgrade from DDR3. It introduces data transfer rates which are nearly double the DDR3 transfer rates, ranging from 1.6 GT/s up to 3.2 GT/s. DDR4's higher transfer rates and lower operating voltage have driven new test methodologies and test requirements which were not previously required for DDR3 in order to ensure proper signal fidelity. QPHY-DDR4 has a full suite of Clock, Electrical, and Timing tests as specified by the JEDEC Specification which will aid in DDR4 design validation.
QPHY-DisplayPort The QPHY-DisplayPort software option provides an automated test environment for running all of the normative real-time oscilloscope tests for sources in accordance with Version 1.2b of the Video Electronics Standards Association (VESA) DisplayPort PHY Compliance Test Specification, as well as tests for HBR3 signals at 8.1 Gbps.
QPHY-eDP QPHY-eDP provides a highly automated and easy-to-use solution for Embedded DisplayPort source testing in accordance with version 1.4 of the VESA Embedded DisplayPort PHY compliance test guideline.
QPHY-ENET Ethernet testing compliant with IEEE 802.3-2005 requires many test setups and connections and mask tests. Using Teledyne LeCroy QualiPHY-ENET these measurements are easy to setup and complete. Instructive connection diagrams and message boxes appear as pop ups on the oscilloscope screen. The connection diagram instructs the user how to change test fixture and jumper pins in order to do complete test. When the tests are complete, QualiPHY will generate a test report in PDF, HTML, or XML formats. Jitter and pulse mask tests are performed with automatic waveform alignment, and all test results feature pass/fail indicators corresponding to the standard being tested.
QPHY-HDMI2 automated and easy-to-use solution for HDMI transmitter testing in accordance with Version 2.0 of the HDMI Compliance Test Specification (including testing for version 1.4 devices).
QPHY-LPDDR2 The Teledyne LeCroy QPHY-LPDDR2 Test Solution is the best way to characterize LPDDR2 memory interfaces. Capable of performing measurements on 466 MHz, 533 MHz, 667 MHz, 800 MHz, 900 Mhz, 1066 MHz and custom speed grades, QPHY-LPDDR2 has a full suite of Clock, Electrical and Timing tests as specified by the JEDEC Specifications.
QPHY-MIPI-DPHY - D-PHY Compliance Package Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the MIPI Alliance Specification for D-PHY version 1.00.00
QPHY-MIPI-MPHY The QPHY-MIPI-MPHY Test Solution provides automated control of Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the MIPI Alliance Specification for M-PHY version 3.0.
QPHY-MOST150 The Teledyne LeCroy QPHY-MOST150 compliance test package provides a highly automated and easy-to-use solution to MOST compliance testing. QPHY-MOST150 will perform all electrical compliance tests as defined in the MOST150 oPHY Automotive Physical Layer Sub-Specification Rev. 1.1 and MOST150 cPHY Automotive Physical Layer Sub-Specification Rev 1.0.
QPHY-MOST50 The Teledyne LeCroy QPHY-MOST50 compliance test package provides a highly automated and easy-to-use solution to MOST compliance testing. QPHY-MOST50 will perform all electrical compliance tests as defined in the MOST Electrical Physical Layer Specification Rev. 1.1.
QPHY-PCIe The Teledyne LeCroy QPHY-PCIe Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing the entire transmitter physical layer tests as described by the Card Electro-mechanical specification Rev 1.1 and 2.0
QPHY-PCIe3 Teledyne LeCroy QPHY-PCIe3 Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the PCI Express Base Specification Revision 3.0 Version 0.9 and the Card Electromechanical Specification Revision 3.0 Version 0.7.
QPHY-SAS2 The Teledyne LeCroy QPHY-SAS2 Test Solution provides automated control for the SDA 8 Zi series of oscilloscopes for performing all of the transmitter physical layer tests as described by version 1.01 of the UNH IOL Serial Attached SCSI (SAS) Consortium SAS-2 6Gb/s Physical Layer Test Suite. This specification covers targets and initiators running at 1.5 Gb/s, 3.0 Gb/s and 6.0 Gb/s.
QPHY-SAS3 The QPHY-SAS3 Test Solution provides automated control of the SDA 8 Zi-A and LabMaster 10 Zi oscilloscopes for performing all of the transmitter physical layer tests as described by the T10 SAS-3 specification. This specification covers targets and initiators running at 1.5 Gb/s, 3.0 Gb/s, 6.0 Gb/s, and 12.0 Gb/s.
QPHY-SATA-TSG-RSG for SATA compliance testing to be used in conjunction with the PeRT3. By leveraging the capabilities of both the oscilloscope and the PeRT3, QPHY-SATA-TSG-RSG can automatically perform all of the PHY, TSG, OOB, and RSG tests as described by the SATA UTD 1.5. Furthermore, QPHY-SATA-TSG can be configured to test Gen1, Gen2, and Gen3 SATA PUTs.
QPHY-SFI The Teledyne LeCroy QPHY-SFI solution automates testing for SFI base on the SFF 8431 specifications. The test framework simplifies the test setup and execution of generic and common test requirements such as jitter separation, rise/fall time and transmitter equalization parameters. The guided wizard prompts the user to for specification required patterns and takes the measurements accordingly. The test report includes the test results pass/fail summary, margins and limits, as well as waveforms and measurements used during the test process.
QPHY-USB The USB package provides a complete acquisition and analysis system for USB 2.0 devices, hosts, and hubs, as specified in the USB-IF USB 2.0 Electrical Test Specification. The test software implements a full set of electrical tests for USB 2.0, including High-, Full-, and Low-speed tests and is supported by Teledyne LeCroy’s QualiPHY automated test and reporting software.
QPHY-USB3-Tx-Rx SuperSpeed USB is one of most highly anticipated standards in several years. At 10x the data rate of USB 2.0 and with new features like CTLE (continuous time linear equalization) and reference channels, SuperSpeed USB will pose new challenges to implementers.
QPHY-USB3.1-Tx-Rx QPHY-USB3.1-Tx-Rx offers an automated test package for USB 3.1 transmitter and receiver compliance testing, characterization, and debug.
WPHD-DDR2-TOOLKIT DDR2 and LPDDR2 Debug Toolkit for WavePro HD
WPHD-DDR3-TOOLKIT DDR3, DDR3L, LPDDR3, DDR2, and LPDDR2 Debug Toolkit for WavePro HD
WPHD-UPG-DDR3-TOOLKIT DDR3, DDR3L, LPDDR3, DDR2, and LPDDR2 Debug Toolkit Upgrade for WavePro HD
Key Features
  • Complete DDR4 test coverage as described by JESD79-4B
  • Support for all standard and custom speed grades
  • Separate bursts using DQ-DQS phase or DDR4 command bus
  • Statistically relevant results achieve measurement confidence
  • Report generation with pass/fail results and fully annotated worst case measurement screenshot
  • DDR Debug Toolkit integration for easy and flexible debug
  • Maximize signal integrity with de-embedding and Virtual Probing

Accurate Burst Separation

Read and Write bursts can be separated based on DQ-DQS phase or based on the command bus when used in conjunction with the HDA125 High-speed Digital Analyzer. The HDA125 enables bursts to be separated using the commands sent from the controller, allowing for accurate burst separation even in situations with non-ideal signal integrity (e.g. reflections).

Measurement Confidence

Due to the high level of variability in DDR measurements, it is important to make statistically relevant measurements to fully characterize DDR4 interfaces. By measuring thousands of cycles in one acquisition, the user can be more confident that they are catching the true maximum and minimum points for their measurement.

Most Flexible DDR4 Debug

QPHY-DDR4 uses the DDR Debug Toolkit to perform all compliance testing. Using the “Stop on Test” feature, the user can pause testing after each individual test and clearly see where the worst case measurement occurred. At that point the DDR Debug toolkit can be leveraged for further debug and upon completion, testing can be seamlessly resumed with one click of a button.

De-embedding and Virtual Probing

Teledyne LeCroy provides software tools which can be used to maximize signal integrity with DDR probing. The VirtualProbe package can virtually move the probe to the DRAM BGA, where it cannot be physical placed, and it will remove any effects of the probe or interposers through de-embedding. The VP@Rcvr (Virtual Probe at Receiver) math function can be used to model the circuit of the DIMM to reduce reflections.

DQ Input Receiver Compliance Mask

For the first time the DDR4 specification includes a compliance mask for the DQ input signal which replaces the traditional DQ setup and hold time measurements. QPHY-DDR4 automatically centers the mask in the DQ eye to test for any mask hits and reports the required shift from the DQS crossing to test tDQS2DQ. This eye diagram is also used to calculate the VIHL_AC peak to peak requirement.

Clock Tests

The DDR4 specification requires clock jitter to be separated into random and deterministic components, which is a first for DDR specifications. QPHY-DDR4 leverages industry leading serial data algorithms to perform the jitter breakdown for tJIT(per). In addition to these tests, QPHY-DDR4 will test average clock period, absolute clock period, average high/low pulse width, absolute high/low pulse width, cycle-cycle jitter, duty cycle jitter, and cumulative error over n period tests.

Timing Tests

tDQSQ verifies the skew between DQS and the associated DQ within a read burst. QPHY-DDR4 will perform this measurement on every DQ transition within a read burst. Upon completion each test will display a fully annotated "worst case measurement" screenshot which includes trace labels for the signals under test and relevant voltage levels.

Electrical Tests

SRI_diff, the DDR4 definition for input slew rate on DQS, measures the slew rate on every rising and falling edge within a write burst. QPHY-DDR4 will measure every transition within each write burst in the acquisition providing statistically meaningful results in a short period of time. In this case over 3,000 slew rate measurements were performed which ensures that the true maximum and minimum points have been caught without requiring multiple acquisitions.