Kibra 380 Analyzer
The Kibra 380 is a stand-alone DDR3 protocol analyzer that provides comprehensive DDR3 bus and JEDEC timing analysis.
The Teledyne LeCroy Kibra 380 is a stand-alone DDR3 protocol analyzer that provides comprehensive DDR3 bus and JEDEC timing analysis. Small and portable, the Kibra 380 is controlled over USB using any Windows-based PC and offers state and timing waveform displays to allow fast debugging of DDR3 systems and memory controllers.
Using non-intrusive slot interposer probes, the system provides loss-less capture of address, command and control signals (ADD/CMD/CNTRL). By focusing on state-based capture and excluding the data signals, the Kibra 380 allows quick analysis of DDR3 transactions. With its high impedance probing and specialized trigger logic, this self-contained solution can monitor a fully loaded memory bus and identify over 65 JEDEC bus event and timing violations in real time.
Text-based decoding of commands including all physical address attributes (RA, CA, BA, CS) allow users to see and verify JEDEC ordering violations.
- Fast and Easy DDR3 Debug
- Self-contained system offers easy connection and setup
- Impedance matched Interposer style probing
- No calibration needed!
- Free trace viewer runs on any PC
- Comprehensive JEDEC Trigger and Capture
- Detects over 65 JEDEC bus event & timing violations in real time
- Extended recording time captures 4X the memory events vs typical Logic Analyzer State listing
- Dedicated trigger output to scope for Read/ Write operations (WE)
- Innovative Displays Focused on Timing Analysis
- Traditional State and Timing Waveform views
- Bus metrics are tracked per bank and per DIMM slot
- Real Time performance displays
- Flexible, Scalable Platform
- Monitor two slots of quad rank DDR3 DIMMS or SO-DIMMs concurrently
- Supports registered buffered and unbuffered DIMM types
- Supports SO-DIMM types (ECC & non-ECC)
The Kibra 380 is the first standalone DDR3 bus analyzer that provides all the essential triggering of a JEDEC pre-processor while simultaneously capturing timing waveforms, decoded state listings, performance, and utilization statistics. Designed specifically to overcome the cost and complexity of monolithic test approaches that rely on logic analyzer platforms, this self-contained solution offers easy connections to system under test.
The Teledyne LeCroy system also features unique, real-time trigger-out to a scope for Read / Write operations (WE). Using this dedicated, low latency SMA trigger out signal, the scope can use the DQ/DQS relationships to distinguish Read / Write operations on the bus.
In addition to timing analysis, the Kibra 380 generates performance metrics that are displayed for read, write, mode register and power down operations. Bus metrics are tracked per bank and per rank to provide insights into overall memory utilization.
Start using the Teledyne LeCroy Kibra 380 immediately without time consuming calibration. Simply enter the memory controller parameters and start recording. The software will automatically load JEDEC timing values for the DIMM type specified. Selectively enable, disable, or customize any of the JEDEC trigger values on-the-fly. Markers are placed at each error event within the Timing view to make it easy to see and verify DDR3 timing.
Small and portable, the Kibra 380 is controlled using any Windows-based PC. It includes the necessary interposer probes capable of monitoring two slots of quad rank DDR3 DIMMs and SO-DIMMs operating to 1600 MT/s. With its unprecedented ease of use, the Kibra 380 solution can replace costly logic analyzer-based debug tools and provide better test coverage at lower overall cost.