The TF-AUTO-ENET is an Automotive Ethernet Breakout Test Fixture to easily separate bidirectional link traffic.
Automotive Ethernet enables faster data communication to meet the demands of today’s vehicles and the connected vehicles of the future. QPHY-1000Base-T1 automates testing and validation of 1 Gb/s Automotive Ethernet, which is described in the 1000Base-T1 (IEEE 802.3bp) specification.
QPHY-USB3.1-Tx-Rx offers an automated test package for USB 3.1 transmitter and receiver compliance testing, characterization, and debug.
The USB package provides a complete acquisition and analysis system for USB 2.0 devices, hosts, and hubs, as specified in the USB-IF USB 2.0 Electrical Test Specification. The test software implements a full set of electrical tests for USB 2.0, including High-, Full-, and Low-speed tests and is supported by Teledyne LeCroy’s QualiPHY automated test and reporting software.
The Teledyne LeCroy QPHY-SFI solution automates testing for SFI base on the SFF 8431 specifications. The test framework simplifies the test setup and execution of generic and common test requirements such as jitter separation, rise/fall time and transmitter equalization parameters. The guided wizard prompts the user to for specification required patterns and takes the measurements accordingly. The test report includes the test results pass/fail summary, margins and limits, as well as waveforms and measurements used during the test process.
for SATA compliance testing to be used in conjunction with the PeRT3. By leveraging the capabilities of both the oscilloscope and the PeRT3, QPHY-SATA-TSG-RSG can automatically perform all of the PHY, TSG, OOB, and RSG tests as described by the SATA UTD 1.5. Furthermore, QPHY-SATA-TSG can be configured to test Gen1, Gen2, and Gen3 SATA PUTs.
The QPHY-SAS3 Test Solution provides automated control of the SDA 8 Zi-A and LabMaster 10 Zi oscilloscopes for performing all of the transmitter physical layer tests as described by the T10 SAS-3 specification. This specification covers targets and initiators running at 1.5 Gb/s, 3.0 Gb/s, 6.0 Gb/s, and 12.0 Gb/s.
The Teledyne LeCroy QPHY-SAS2 Test Solution provides automated control for the SDA 8 Zi series of oscilloscopes for performing all of the transmitter physical layer tests as described by version 1.01 of the UNH IOL Serial Attached SCSI (SAS) Consortium SAS-2 6Gb/s Physical Layer Test Suite. This specification covers targets and initiators running at 1.5 Gb/s, 3.0 Gb/s and 6.0 Gb/s.
Teledyne LeCroy QPHY-PCIe3 Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the PCI Express Base Specification Revision 3.0 Version 0.9 and the Card Electromechanical Specification Revision 3.0 Version 0.7.
The Teledyne LeCroy QPHY-PCIe Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing the entire transmitter physical layer tests as described by the Card Electro-mechanical specification Rev 1.1 and 2.0
The Teledyne LeCroy QPHY-MOST50 compliance test package provides a highly automated and easy-to-use solution to MOST compliance testing. QPHY-MOST50 will perform all electrical compliance tests as defined in the MOST Electrical Physical Layer Specification Rev. 1.1.
The Teledyne LeCroy QPHY-MOST150 compliance test package provides a highly automated and easy-to-use solution to MOST compliance testing. QPHY-MOST150 will perform all electrical compliance tests as defined in the MOST150 oPHY Automotive Physical Layer Sub-Specification Rev. 1.1 and MOST150 cPHY Automotive Physical Layer Sub-Specification Rev 1.0.
The QPHY-MIPI-MPHY Test Solution provides automated control of Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the MIPI Alliance Specification for M-PHY version 3.0.
QPHY-MIPI-DPHY - D-PHY Compliance Package
Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the MIPI Alliance Specification for D-PHY version 1.00.00
The Teledyne LeCroy QPHY-LPDDR2 Test Solution is the best way to characterize LPDDR2 memory interfaces. Capable of performing measurements on 466 MHz, 533 MHz, 667 MHz, 800 MHz, 900 Mhz, 1066 MHz and custom speed grades, QPHY-LPDDR2 has a full suite of Clock, Electrical and Timing tests as specified by the JEDEC Specifications.
automated and easy-to-use solution for HDMI transmitter testing in accordance with Version 2.0 of the HDMI Compliance Test Specification (including testing for version 1.4 devices).
Ethernet testing compliant with IEEE 802.3-2005 requires many test setups and connections and mask tests. Using Teledyne LeCroy QualiPHY-ENET these measurements are easy to setup and complete. Instructive connection diagrams and message boxes appear as pop ups on the oscilloscope screen. The connection diagram instructs the user how to change test fixture and jumper pins in order to do complete test. When the tests are complete, QualiPHY will generate a test report in PDF, HTML, or XML formats. Jitter and pulse mask tests are performed with automatic waveform alignment, and all test results feature pass/fail indicators corresponding to the standard being tested.
QPHY-eDP provides a highly automated and easy-to-use solution for Embedded DisplayPort source testing in accordance with version 1.4 of the VESA Embedded DisplayPort PHY compliance test guideline.
The QPHY-DisplayPort software option provides an automated test environment for running all of the normative real-time oscilloscope tests for sources in accordance with Version 1.2b of the Video Electronics Standards Association (VESA) DisplayPort PHY Compliance Test Specification, as well as tests for HBR3 signals at 8.1 Gbps.
DDR4 is an evolutionary upgrade from DDR3. It introduces data transfer rates which are nearly double the DDR3 transfer rates, ranging from 1.6 GT/s up to 3.2 GT/s. DDR4's higher transfer rates and lower operating voltage have driven new test methodologies and test requirements which were not previously required for DDR3 in order to ensure proper signal fidelity. QPHY-DDR4 has a full suite of Clock, Electrical, and Timing tests as specified by the JEDEC Specification which will aid in DDR4 design validation.
The Teledyne LeCroy QPHY-DDR3 Test Solution is the best way to characterize DDR3, DDR3L, and LPDDR3 memory interfaces. Capable of performing measurements on 800 MT/s, 1066 MT/s, 1333 MT/s, 1600 MT/s, 1866 MT/s, 2133 MT/s and custom speed grades, QPHY-DDR3 has a full suite of Clock, Electrical, and Timing tests as specified by the JEDEC Specification.
The Teledyne LeCroy QPHY-DDR2 Test Solution is the best way to characterize DDR2 memory interfaces. Capable of performing measurements on 400 MHz, 533 MHz, 667 MHz, 800 MHz, 1066 MHz and custom speed grades, QPHY-DDR2 has a full suite of Clock, Electrical and Timing tests as specified by the JEDEC Specification and Intel JEDEC Specifications Addendums.
QPHY-10GBASE-T automated compliance test software performs electrical compliance testing of the Physical Media Attachment (PMA) for 10GBASE-T Ethernet PHY, based on IEEE802.3-2008 requirements.
The Teledyne LeCroy QPHY-10GBase-KR solution automates testing for 10Gigabite Ethernet Copper Backplane base on the IEEE 802.3ap specifications. The test framework simplifies the test setup and execution of generic and common test requirements such as jitter separation, rise/fall time and transmitter equalization parameters. The guided wizard prompts the user to for specification required patterns and takes the measurements accordingly. The test report includes the test results pass/fail summary, margins and limits, as well as waveforms and measurements used during the test process.
Low Noise Edge Shaper
GRL-USB-PD-C1 is a flexible test controller, designed for USB-PD Compliance testing of the Unit Under Test (UUT) and more.
GRL-USB-PD software provides a simple and efficient way to perform USB-PD electrical parametric and protocol measurements. GRL-USB-PD provides waveform visibility and protocol analysis making it ideal for design and debug of USB Type-C Power Delivery silicon and end products.
Electrical Telecom Mask Test Package
DDR Debug Toolkit
The DDR Debug Toolkit provides test, debug and analysis tools for the entire DDR design cycle. The unique DDR analysis capabilities provide automatic Read and Write burst separation, bursted data jitter analysis and DDR-specific measurement parameters.
Automotive Ethernet enables faster data communication to meet the demands of today’s vehicles and the connected vehicles of the future. QPHY-BroadR-Reach automates testing and validation of 100 Mb/s Automotive Ethernet, which is described in both the BroadR-Reach and 100Base-T1 (IEEE 802.3bw) specifications.
Read/Write Bursts Separation
- Read/Write burst separation with a push of a button
- Simultaneous analysis of four different measurement scenarios
- View up to 10 eye diagrams with mask testing and eye measurements
- Perform jitter analysis for root cause analysis
- Quickly configure measurements specific to DDR
- Analyze specific regions of bursts with configurable qualifiers
- Support for DDR2/3/4 and LPDDR2/3
- Select standard and custom speed grades
Automatically separate Read and Write bursts with the DDR Debug Toolkit, eliminating the time consuming process of manual burst identification and simplifying the analysis of DDR system performance and validation.
View Up to 10 Eye Diagrams Simultaneously
The DDR Debug Toolkit can quickly create and display up to 10 eye diagrams simultaneously with a push of a button. Visual inspection and analysis of side-by-side eye diagrams can provide valuable skew and timing information. Choosing to have CK or DQS as the timing reference provides two different vantage points of system performance.
Eye Diagram Analysis
Using the DDR Debug Toolkit any DQ, DQS or address signal can be tested against a standard or a custom defined mask. Enabling mask failure indicators will automatically identify any mask violations. Built-in measurements such as eye height, eye width and eye opening are critical to gaining a quantitative understanding of the system performance. With simultaneous eye measurements it is easy to compare performance across multiple testing scenarios.
DDR Jitter Analysis
Bursted DDR signals create undesirable complications and challenges for traditional serial data analysis and jitter tools preventing analysis of DQ, DQS and address signals. Jitter parameters including Tj, Rj, and Dj are calculated across all active DDR measurement scenarios. To gain a deeper understanding of the jitter distribution, traditional displays such as TIE histograms, TIE track, and bathtub curves are available.
With a toolbox of parameters specific to DDR it is simple to quickly configure insightful measurements for validation, characterization, and debug. Up to 12 configurable measurements can be displayed and analyzed simultaneously across all active measurement scenarios. For each measurement, advanced statistics such as min, max, mean, and number of measurement instances can be displayed.
Four Measurement Scenarios
When configuring a measurement scenario each scenario can be independently assigned a signal to be analyzed, providing extensive flexibility for analysis. For example, it is simple to setup a comparison of system performance between read and write burst operation across multiple DQ lanes. Simultaneous analysis of up to four measurement scenarios simplifies the measurement process and eliminates concerns about making unsynchronized measurements.
Reference Scenario for Optimization Testing
The Reference Scenario allows engineers to easily conduct performance tuning or optimization tests. The user is able to store any measurement scenario into a reference scenario, then make a change to their setup to observe a change in any performance characteristics. Measurements can be added or removed from the reference scenario at any time so there is no need to worry about having all analysis parameters defined at the beginning of testing.
Analyze Isolated Regions of Bursts
Using built-in configurable qualifiers, all of the analysis in the DDR Debug Toolkit can be gated to include or ignore the first “n” bits. This allows for a deep understanding of how the system is performing under specific conditions. For example, this type of analysis can be used to gain knowledge about how the system is functioning coming out of preamble or exclusively in the middle of burst operation.