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SATA (Serial ATA)

SATA (Serial ATA)

Serial ATA (SATA) is a data transfer technology designed to move data to and from storage devices such as disk drives, ATAPI drives, host bus adapters (HBA), and port multipliers. SATA is a serialized enhancement and replacement to parallel IDE. Since SATA ratification in 2003 and its move to 6Gbps in 2008, Teledyne LeCroy has continued to support and innovate with its industry leading protocol analysis and traffic generation capabilities.
SATA Sierra M6-2 The Sierra Protocol Test System is the 6th generation in the leading line of SATA protocol test solutions from the leading manufacturer of protocol test systems. Designed for the current evolution of SATA (SATA 3.0), the new Sierra product family sets new standards for performance while incorporating a complete range of features in a single, economical system.
SATA Sierra M6-1 SATA Protocol Test System
Serial ATA Test and Verification: Teledyne LeCroy's protocol analysis tools are designed from the ground up to address these unique characteristics of Serial ATA. Teledyne LeCroy's analysis and design suites are developed specifically for use with the SAS and SATA protocols, and provide extensive protocol decoding, expert error analysis, and complete user support when decoding and viewing the recorded traffic. This extensive protocol support, combined with the different traffic views, advanced triggering, data filtering, traffic generation, and error injection capability, allows engineers to rapidly become familiar with SATA-specific issues, and quickly understand new issues the first time they encounter them.
Teledyne LeCroy provides everything needed for Serial ATA analysis including real-time hardware triggering and filtering on the critical components of Serial ATA traffic. Teledyne LeCroy's Expert Analysis software simplifies the overall debug process by using collapsible, color-coded packets to represent commands, FISs and primitives. This provides point-and-click "drill down" to lower level details along with the ease of use and understanding that Teledyne LeCroy is well known for.
Learn more about SATA (Serial ATA)Technology

SATA (Serial ATA) Overview
The storage industry is in the midst of a large-scale transition from parallel ATA, the dominant desktop storage interface, to Serial ATA. This migration reflects a broader transition across the industry to Serial technologies for computer-based communications. Driven primarily by lower voltages and costs required in future chipsets, Serial ATA is poised for industry-wide adoption. The specification thoughtfully preserves software compatibility with the Parallel ATA command set. What's more, it offers smaller, thinner, lower cost cables that also offer compatibility at the physical layer with the emerging Serial Attached SCSI (SAS) standard.
Features
  • Performance - Parallel ATA does not have scalability to support several more speed doublings, and it is nearing its performance capacity. By contrast, Serial ATA defines a roadmap starting at 1.5 gigabits per second (equivalent to a data rate of 150 MB/s) up to 6Gigabits per second.
  • Lower Voltage - Parallel ATA's 5-volt signaling requirement will be increasingly difficult to meet as the industry continues to reduce chip core voltages. Serial ATA is better aligned with future manufacturing processes. It reduces signaling voltages to approximately 250 millivolts (1/4 volt).
  • Pin Count - Currently, the parallel ATA interface has 26 signal pins going into the interface chip. Serial ATA uses only 4 signal pins, improving the pin efficiency and accommodating a highly integrated chip implementation.
  • Improved Cabling - Parallel ATA bulky ribbon cables contain 40-pin header connector. Serial ATA introduces thin, flexible cabling scheme that offers longer cables and improved airflow within the chassis.
  • Software Compatible - Serial ATA is compatible at the register level with parallel ATA. This means Serial ATA requires no changes to existing software and operating systems in order to function, and it provides backward compatibility with existing operating environments.
  • SAS Compatibility - A significant feature offered by Serial ATA is the expectation that SATA will be form-factor compatibility with Serial Attached SCSI. SATA drives will plug directly into Serial Attached SCSI connectors and if supported in the system, will transparently operate as a SATA device. This allows systems to be deployed that can use either Serial Attached SCSI drives, for their high performance or SATA drives that will provide a lower-cost-per-megabyte storage platform.
  • SATA DevSleep™ - The latest SATA 3.2 specification includes DevSleep, a new feature designed to reduce power consumption and allow longer battery life as well as energy savings in the data center. It re-uses the 3.3V power pin on the SATA interface to instruct the device to enter the Sleep state where it uses less power than Slumber mode. With most low power modes, this new feature requires extensive testing at the protocol layer to ensure a seamless user experience.

Architecture
  • Serial ATA is a full duplex protocol. There is a continuous flow of signals from each device moving down the bus. The device and host are transmitting (TX) and receiving (RX) at the same time.
  • Bidirectional traffic pattern eliminates the need for bus negotiation overhead
  • Data characters vs Primitives - Primitives are the simplest elements within the Serial ATA protocol. Primitives are 32-bit DWORDs used to initiate control of the serial line functions (X_RDY, CONT, etc...). In addition to these "handshaking" and flow control signals, Primitives are also used to delimit or "frame" user data.
  • Frame Information Structure (FIS) - A frame is an indivisible unit of information exchanged between a host and device. A frame consists of a SOF primitive, a Frame Information Structure (FIS), a CRC calculated over the contents of the FIS, and an EOF primitive. A FIS is the user payload of a frame; a frame is a group of Dwords that convey information between host and device as described previously.

Links

Serial ATA Test and Verification: Teledyne LeCroy's protocol analysis tools are designed from the ground up to address these unique characteristics of Serial ATA. Teledyne LeCroy's analysis and design suites are developed specifically for use with the SAS and SATA protocols, and provide extensive protocol decoding, expert error analysis, and complete user support when decoding and viewing the recorded traffic. This extensive protocol support, combined with the different traffic views, advanced triggering, data filtering, traffic generation, and error injection capability, allows engineers to rapidly become familiar with SATA-specific issues, and quickly understand new issues the first time they encounter them.
Teledyne LeCroy provides everything needed for Serial ATA analysis including real-time hardware triggering and filtering on the critical components of Serial ATA traffic. Teledyne LeCroy's Expert Analysis software simplifies the overall debug process by using collapsible, color-coded packets to represent commands, FISs and primitives. This provides point-and-click "drill down" to lower level details along with the ease of use and understanding that Teledyne LeCroy is well known for.
Learn more about SATA (Serial ATA)Technology

SATA (Serial ATA) Overview
The storage industry is in the midst of a large-scale transition from parallel ATA, the dominant desktop storage interface, to Serial ATA. This migration reflects a broader transition across the industry to Serial technologies for computer-based communications. Driven primarily by lower voltages and costs required in future chipsets, Serial ATA is poised for industry-wide adoption. The specification thoughtfully preserves software compatibility with the Parallel ATA command set. What's more, it offers smaller, thinner, lower cost cables that also offer compatibility at the physical layer with the emerging Serial Attached SCSI (SAS) standard.
Features
  • Performance - Parallel ATA does not have scalability to support several more speed doublings, and it is nearing its performance capacity. By contrast, Serial ATA defines a roadmap starting at 1.5 gigabits per second (equivalent to a data rate of 150 MB/s) up to 6Gigabits per second.
  • Lower Voltage - Parallel ATA's 5-volt signaling requirement will be increasingly difficult to meet as the industry continues to reduce chip core voltages. Serial ATA is better aligned with future manufacturing processes. It reduces signaling voltages to approximately 250 millivolts (1/4 volt).
  • Pin Count - Currently, the parallel ATA interface has 26 signal pins going into the interface chip. Serial ATA uses only 4 signal pins, improving the pin efficiency and accommodating a highly integrated chip implementation.
  • Improved Cabling - Parallel ATA bulky ribbon cables contain 40-pin header connector. Serial ATA introduces thin, flexible cabling scheme that offers longer cables and improved airflow within the chassis.
  • Software Compatible - Serial ATA is compatible at the register level with parallel ATA. This means Serial ATA requires no changes to existing software and operating systems in order to function, and it provides backward compatibility with existing operating environments.
  • SAS Compatibility - A significant feature offered by Serial ATA is the expectation that SATA will be form-factor compatibility with Serial Attached SCSI. SATA drives will plug directly into Serial Attached SCSI connectors and if supported in the system, will transparently operate as a SATA device. This allows systems to be deployed that can use either Serial Attached SCSI drives, for their high performance or SATA drives that will provide a lower-cost-per-megabyte storage platform.
  • SATA DevSleep™ - The latest SATA 3.2 specification includes DevSleep, a new feature designed to reduce power consumption and allow longer battery life as well as energy savings in the data center. It re-uses the 3.3V power pin on the SATA interface to instruct the device to enter the Sleep state where it uses less power than Slumber mode. With most low power modes, this new feature requires extensive testing at the protocol layer to ensure a seamless user experience.

Architecture
  • Serial ATA is a full duplex protocol. There is a continuous flow of signals from each device moving down the bus. The device and host are transmitting (TX) and receiving (RX) at the same time.
  • Bidirectional traffic pattern eliminates the need for bus negotiation overhead
  • Data characters vs Primitives - Primitives are the simplest elements within the Serial ATA protocol. Primitives are 32-bit DWORDs used to initiate control of the serial line functions (X_RDY, CONT, etc...). In addition to these "handshaking" and flow control signals, Primitives are also used to delimit or "frame" user data.
  • Frame Information Structure (FIS) - A frame is an indivisible unit of information exchanged between a host and device. A frame consists of a SOF primitive, a Frame Information Structure (FIS), a CRC calculated over the contents of the FIS, and an EOF primitive. A FIS is the user payload of a frame; a frame is a group of Dwords that convey information between host and device as described previously.

Links

Sierra SATA Host and Device Emulation

0309_sierra_with_initiator_under_test_lg.jpg0309_sierra_with_target_under_test_lg.jpg

Teledyne LeCroy's Sierra and STX platforms are the only test systems that are capable of emulating SATA traffic up to 6Gb/s. The Sierra can emulate either the host or device side, enabling developers to accelerate their product cycles ahead of industry-wide adoption. Without other devices to test interoperability, designers are left to develop expensive and resource-consuming in-house platforms that rarely cover the full spectrum of testing needed. With the Sierra, engineers have a complete turnkey test system that can be used with a large, pre-programmed library of test scripts, or easily create customized tests for their specific product.

For complete product testing at the protocol level, the Sierra's Host emulator can run at 1.5G, 3G, or 6G line speeds and automatically perform CRC generation, 8b/10b encoding, and data scrambling. Link layer protocol exchanges, handshaking, OOB sequencing, and retry conditions are handled automatically, but can also be manipulated to create various error scenarios, such as speed negotiation window (SNW) failures, buffer over/under run, CRC errors, and timeout conditions. The Host emulator can be operated at the command, frame and primitive levels.sata_hostgenerator.png

Serial ATA Protocol Compliance

The Sierra features an option for the integrated Serial ATA (SATA) Compliance Test Suite. Testing includes support for disk drives, including HDD, SSD, ATAPI and M.2 based SATA drives. Areas addressed by the Compliance Test Suite include Asynchronous Signal Recovery (ASR), Interface Power Management (IPM), General Test Requirements (GTR), Software Settings Preservation (SSP), and Native Command Queuing (NCQ). The SATA (target side) Compliance Tests are ratified for logo testing by the SATA-IO Compliance Working Group.

The SATA Compliance Test Suite is fully automated and can be used for regression testing. After the test suite has completed running, a report is generated with test results. Traces are saved for all tests such that the end-user can verify potential design issues. The SATA Compliance Test Suite can is an optional feature for the Sierra M6-2 or M6-4 platforms.

Sierra SATA Traffic Generator

The Sierra M6-2 & M6-4 platform provides a 6Gbps SATA Traffic Generator option. The script-based traffic generator gives engineers the ability to control the SATA traffic stream down to the bit level, including flexibility for changing OOB waveforms, programmatically delaying handshake primitives, and transmitting user-defined data patterns for customized testing throughout the design process.

Using previously recorded SATA traffic files (.SATA) it's possible to export either host or device side transmissions to the generator file format. This allows validation engineers to easily recreate problems reported in the field using a trace file. Any sequence of SATA packets captured with the Sierra analyzer can be edited and then played back as a test pattern using the Sierra traffic generator.

Sierra also offers a text-based API for creating scripts from the ground up. This mode is ideal for performing corner-case, stress and limit testing. It can also be used to validate protocol compliance and fault handling by injecting code violations, CRC, scrambling and protocol errors, or customized data payloads.sata_emulation.png

SATA "handshaking" are global settings that allow the Sierra to automatically reply to out-of-band, speed negotiation signals, HOLD, XRDY, RRDY and other primitives. When enabled in a script, they allow the Sierra to independently respond to bus events that require low-latency handshakes. The scripting API provides full control for adding delay to automatic handshaking to help validate state machine transitions on the DUT. The Traffic Generator also supports unlimited levels of IF-THEN-ELSE logic which can be added to a script and allow the exerciser to conditionally respond to inbound frames or data patterns. This expands the range of tests that can be completed with Sierra by enabling longer exchanges with larger test configurations.

Sierra SATA Error Injector (InFusion™)

Building on the capabilities of the industry's first SAS/SATA error injection system, the InFusion™ option for the Sierra M6-2 & M6-4 platforms can programmatically alter or corrupt traffic for both SATA 6G and SAS 6G protocols. Fully integrated within the Sierra analyzer, Infusion is designed to create faulty link conditions while the analyzer records the real response from the system under test. The InFusion solution is the ideal tool for stress testing systems while running real traffic and actual workloads.

Powerful Error Injection and Traffic Modification Abilities
Once the Sierra InFusion system has been added to a SAS or SATA link, it automatically passes the boot up sequence and preserves protocol handshaking between devices. It silently monitors the line while transmitting a faithful copy of the original data stream. The system will wait for a specific time interval or a specific event before it begins modifying frames or injecting errors. The InFusion system can be configured to send a single error, multiple errors, or random errors.

When changing fields within a frame, the Sierra InFusion traffic modifier will preserve the outbound frame structure, including recalculating the CRC if needed. The response transmitted from the device-under-test will pass through the Sierra system, without modification. This allows true end-to-end system testing.

Use Jammer and Analyzer simultaneously
The Sierra Infusion system can operate on up to four SAS or SATA links simultaneously using the M6-4 platform (two links on the M6-2). Most users will elect to use the Sierra analyzer simultaneously to capture traffic after the error is injected to verify recovery (not required). The Flexport feature allows "Analyzer-Jammer-Analyzer" (AJA) mode where the analyzer captures traffic both before and after the error over a single host-device connection.

Flexible and Easy to Use
In just minutes, an easy-to-use pop up menu interface makes it easy to create test scenarios. Any primitive, FIS or data pattern can be intercepted and changed to a user defined pattern. From dropping entire packets, to changing any field within a frame, the Infusion system can create data integrity or simple handshaking errors. This allows for unprecedented corner case and protocol level stress testing for SAS and SATA traffic.sata-infusion.png

The Sierra InFusion system is designed to modify traffic between a real host and target, which better reflects real world operating conditions compared to script based emulation. Jammer test scenarios are independent of the hardware setup and rarely need to be tuned for different configurations. Saved test scenarios can be recalled making it easy to re-verify recovery behaviors during regression testing of software or firmware.

Sophisticated error injection strategies are now possible using dual sequencers with up to 256 sequential wait states per sequence. Each state can be configured to check for different conditions or inject different errors before branching to the next state. Looping allows the error injection sequence to repeat at specific intervals. Each sequential state can also include timers and counters to better isolate specific link conditions.

A Comprehensive Solution for SAS and SATA
Teledyne LeCroy's SAS and SATA solutions provide the advanced features needed to deliver the most reliable and robust storage solutions available. By combining the functionality of the Sierra Analyzer, Traffic Generator, and Error Injector, users can perform comprehensive, end-to-end verification of storage subsystems.

Sierra External Power Expansion Card v2

The Sierra External Power Expansion Card v2 combines configurable AC power supply for the DUT with the CATC Sync port. Specifically designed for powering SAS/SATA HDD/SSDs during Sierra Emulator or Trainer test sessions, the Power Expansion card can also be used in analyzer mode to graphically display power consumption used by the device. Special support for SATA DevSleep allows real time verification of low power behaviors, by allowing control and monitoring of the DevSleep signal. The card is easily installed by the user and is compatible with the Sierra M6-2, M6-4, M124, and M122.sierra_power_expansion_01.png

Power Expansion card (model: ACC-EXP-005-X) includes custom cables below:
  • 15 pin Sata Power Cable
  • 4 pin Sata Power Cable
  • Analyzer mode SATA DevSlp Cable, which includes :
    • 1 DevSlp wire to solder or clip to the DevSlp pin of the Host or DUT
    • 1 Gnd wire to solder or clip to the Gnd pin of the Host or DUT
    • Solder tips and Gripper Clips

CrossSync Multi-Protocol Analysis option

CrossSync is Teledyne LeCroy's analyzer synchronization solution that enables time-aligned display of protocol traffic from multiple daisy-chained analyzers. Captured packets are displayed in separate windows that share a common time scale. Navigating the traffic in either direction will scroll to the same timestamp in the synchronized window. When using the CrossSync option, users can access the full complement of analysis capabilities available within each individual Teledyne LeCroy software. Search, reporting, and decoding all operate normally.

Identifying the point where a specific bus event moves over a bridge is nearly impossible without the CrossSync synchronization solution. Now it's easy to use triggering to find the same packet travelling across both busses. Either analyzer can be set up as the trigger master. When the trigger event is detected, the capture on all daisy chained analyzers stops, Each display will show the exact point where the event occurred. It's also possible to define separate trigger events that operate independently for each side of the bridge.

The solution includes a lightweight software control panel that starts and stops recording across daisy-chained analyzers. Users can sync or un-synch traces on-the-fly. The Time Tune feature provides a real time slider for adjusting the offset between displays. This makes it easy to see latency across busses.

The CrossSync control panel is available at no cost and only requires the analyzers to be connected using their on-board Sync ports. This Sync port is built-in to every Advisor T3 and STX M6-1 analyzer. For owners of Teledyne LeCroy's, Summit T3, Voyager M3i, and Sierra -based analyzers, the Sync port is available as an optional expansion board (ACC-EXP-002-X) that can be installed by users in just a few minutes. This allows developers to leverage analyzers already in the lab to help resolve multi-protocol problems at the system level.

The CrossSync option supports a wide combination of Teledyne LeCroy's flagship analyzers including PCI Express Gen 1, Gen 2 and Gen 3, USB 2.0 and 3.0, Serial ATA (SATA) 1.5, 3, and 6Gbps, Serial Attached SCSI 6Gbps, and Fibre Channel 1, 2, 4 and 8Gbps systems.