DDR3 & DDR4
Новаторский подход Teledyne LeCroy к последовательному представлению данных были использованы разработчиками компьютерных систем и периферийных устройств в течение более 15 лет. С его введением новой низкой стоимости испытательной платформы для DDR3 и DDR4, Teledyne LeCroy теперь приносит свою высокую скорость зондирования и анализа опыта для разработчиков систем памяти высокой производительности.
Kibra 480 Analyzer
The Kibra 480 is a stand-alone protocol analyzer that provides comprehensive bus and JEDEC timing analysis for DDR3 and DDR4. Sitting in-line on a live system, the analyzer uses a proprietary probe implementation to allow loss-less capture of high speed DDR transactions while automatically identifying timing and protocol violations.
DDR is the acronym for Double Data-Rate Synchronous DRAM (SDRAM) and is the terminology used to describe memory used on modern computer systems. It is the successor of PC100/133 SDRAM which was primarily used prior to 1999. DDR was first introduced in 2000 and the primary advantage was its ability to fetch data on both the rising and falling edge of a clock cycle, doubling the data rate for a given clock frequency. For example, in a DDR200 device the data transfer frequency is 200 MHz, but the bus speed is 100 MHz. The DDR memory bus runs at the clock rate of 100 MHz for PC1600, 133 MHz for PC2100, 166 MHz for PC2700 and 200MHz for PC3200. However, each DDR memory module and memory chip run at an effective (data) rate of 200 MHz, 266 MHz, 333 MHz and 400MHz respectively. The computer industry has adopted a practical convention of just referring to the data rate as the DDR DIMM speed. So, PC1600 DIMMs are said to run at 200 MHz, PC2100 DIMMs at 266 MHz and so on.
Like all PC technologies, memory performance and density continue to evolve to meet the demands of faster CPUs. DDR2 was designed to deliver higher overall throughput, the main difference between DDR and DDR2 DRAM is that for DDR2 the memory cells are clocked at 1 quarter the rate of the bus. DDR2 RAM's bus frequency is boosted by electrical interface improvements, on-die termination, pre-fetch buffers and off-chip drivers. DDR2 RAM memory also uses a new form factor, a 240 pin DIMM (Dual Inline Memory Module) that is not compatible with the DDR1 standard.
The newest DDR memory interface technology, DDR3, offers significant advantages over previous DDR generations. DDR3 supports data rates up to 1600 Mbps per pin with an operating voltage of 1.5 volts, a 17% reduction from the previous generation of DDR2, which operates at 1.8 volts. DDR3's built-in power conservation features, like partial refresh are desirable for mobile applications where battery power will no longer be needed just to refresh a portion of the DRAM not in active use. DDR3 also has a specification for an optional thermal sensor that allow mobile engineers to save further power by providing minimum refresh cycles.
Since DDR3 is designed to run at higher memory speeds the signal integrity of the memory module is now more important. DDR3 uses "fly-by" routing instead of the "T branches" seen on DDR2 modules. This means the address and control lines are a single path chaining from one DRAM to another, where DDR2 uses a T topology that branches on DDR2 modules. "Fly-by" takes away the mechanical line balancing and uses automatic signal time delay generated by the controller fixed at the memory system training. Each DDR3 DRAM chip has an automatic leveling circuit for calibration and to memorize the calibration data. DDR3 also uses more internal banks - 8 instead of the 4 used by DDR2 - to further speed up the system. More internal banks allow advance prefetch to reduce access latency.
All DDR memory access are burst oriented where an access starts at a selected location and continues for the burst amount. As an added complexity, Intel memory design uses interleaved burst type; with most other controllers using sequential burst type. The ability to distinguish between interleaved and sequential bursts during testing is a critical distinction when triggering on timing violations. Other complexities introduced with DDR3 include signal integrity testing on the Data lines. Because DQ/DQS are bidirectional, developers must use the DQ/DQS relationships to distinguish between Read / Write operations on the bus. Teledyne LeCroy's Kibra analyzer helps address this test challenge using dedicated, low latency SMA trigger-out to a scope for Read and Write operations (WE).
Demand from real time system developers will continue to push the evolution of memory to meet the need for improved performance, density and power efficiency.
Like all PC technologies, memory performance and density continue to evolve to meet the demands of faster CPUs. DDR2 was designed to deliver higher overall throughput, the main difference between DDR and DDR2 DRAM is that for DDR2 the memory cells are clocked at 1 quarter the rate of the bus. DDR2 RAM's bus frequency is boosted by electrical interface improvements, on-die termination, pre-fetch buffers and off-chip drivers. DDR2 RAM memory also uses a new form factor, a 240 pin DIMM (Dual Inline Memory Module) that is not compatible with the DDR1 standard.
| DDR2 | DDR3 | |
| Rated Speed | 400-800 Mbps | 800-1600 Mbps |
| Vdd/Vddq | 1.8V +/- 0.1V | 1.5V +/- 0.075V |
| Internal Banks | 4 | 8 |
| Termination | Limited | All DQ signals |
| Topology | Conventional T | Fly-by |
| Driver Control | OCD Calibration | Self Calibration with ZQ |
| Thermal Sensor | No | Yes (Optional) |
The newest DDR memory interface technology, DDR3, offers significant advantages over previous DDR generations. DDR3 supports data rates up to 1600 Mbps per pin with an operating voltage of 1.5 volts, a 17% reduction from the previous generation of DDR2, which operates at 1.8 volts. DDR3's built-in power conservation features, like partial refresh are desirable for mobile applications where battery power will no longer be needed just to refresh a portion of the DRAM not in active use. DDR3 also has a specification for an optional thermal sensor that allow mobile engineers to save further power by providing minimum refresh cycles.
Since DDR3 is designed to run at higher memory speeds the signal integrity of the memory module is now more important. DDR3 uses "fly-by" routing instead of the "T branches" seen on DDR2 modules. This means the address and control lines are a single path chaining from one DRAM to another, where DDR2 uses a T topology that branches on DDR2 modules. "Fly-by" takes away the mechanical line balancing and uses automatic signal time delay generated by the controller fixed at the memory system training. Each DDR3 DRAM chip has an automatic leveling circuit for calibration and to memorize the calibration data. DDR3 also uses more internal banks - 8 instead of the 4 used by DDR2 - to further speed up the system. More internal banks allow advance prefetch to reduce access latency.
All DDR memory access are burst oriented where an access starts at a selected location and continues for the burst amount. As an added complexity, Intel memory design uses interleaved burst type; with most other controllers using sequential burst type. The ability to distinguish between interleaved and sequential bursts during testing is a critical distinction when triggering on timing violations. Other complexities introduced with DDR3 include signal integrity testing on the Data lines. Because DQ/DQS are bidirectional, developers must use the DQ/DQS relationships to distinguish between Read / Write operations on the bus. Teledyne LeCroy's Kibra analyzer helps address this test challenge using dedicated, low latency SMA trigger-out to a scope for Read and Write operations (WE).
Demand from real time system developers will continue to push the evolution of memory to meet the need for improved performance, density and power efficiency.
DDR is the acronym for Double Data-Rate Synchronous DRAM (SDRAM) and is the terminology used to describe memory used on modern computer systems. It is the successor of PC100/133 SDRAM which was primarily used prior to 1999. DDR was first introduced in 2000 and the primary advantage was its ability to fetch data on both the rising and falling edge of a clock cycle, doubling the data rate for a given clock frequency. For example, in a DDR200 device the data transfer frequency is 200 MHz, but the bus speed is 100 MHz. The DDR memory bus runs at the clock rate of 100 MHz for PC1600, 133 MHz for PC2100, 166 MHz for PC2700 and 200MHz for PC3200. However, each DDR memory module and memory chip run at an effective (data) rate of 200 MHz, 266 MHz, 333 MHz and 400MHz respectively. The computer industry has adopted a practical convention of just referring to the data rate as the DDR DIMM speed. So, PC1600 DIMMs are said to run at 200 MHz, PC2100 DIMMs at 266 MHz and so on.
Like all PC technologies, memory performance and density continue to evolve to meet the demands of faster CPUs. DDR2 was designed to deliver higher overall throughput, the main difference between DDR and DDR2 DRAM is that for DDR2 the memory cells are clocked at 1 quarter the rate of the bus. DDR2 RAM's bus frequency is boosted by electrical interface improvements, on-die termination, pre-fetch buffers and off-chip drivers. DDR2 RAM memory also uses a new form factor, a 240 pin DIMM (Dual Inline Memory Module) that is not compatible with the DDR1 standard.
The newest DDR memory interface technology, DDR3, offers significant advantages over previous DDR generations. DDR3 supports data rates up to 1600 Mbps per pin with an operating voltage of 1.5 volts, a 17% reduction from the previous generation of DDR2, which operates at 1.8 volts. DDR3's built-in power conservation features, like partial refresh are desirable for mobile applications where battery power will no longer be needed just to refresh a portion of the DRAM not in active use. DDR3 also has a specification for an optional thermal sensor that allow mobile engineers to save further power by providing minimum refresh cycles.
Since DDR3 is designed to run at higher memory speeds the signal integrity of the memory module is now more important. DDR3 uses "fly-by" routing instead of the "T branches" seen on DDR2 modules. This means the address and control lines are a single path chaining from one DRAM to another, where DDR2 uses a T topology that branches on DDR2 modules. "Fly-by" takes away the mechanical line balancing and uses automatic signal time delay generated by the controller fixed at the memory system training. Each DDR3 DRAM chip has an automatic leveling circuit for calibration and to memorize the calibration data. DDR3 also uses more internal banks - 8 instead of the 4 used by DDR2 - to further speed up the system. More internal banks allow advance prefetch to reduce access latency.
All DDR memory access are burst oriented where an access starts at a selected location and continues for the burst amount. As an added complexity, Intel memory design uses interleaved burst type; with most other controllers using sequential burst type. The ability to distinguish between interleaved and sequential bursts during testing is a critical distinction when triggering on timing violations. Other complexities introduced with DDR3 include signal integrity testing on the Data lines. Because DQ/DQS are bidirectional, developers must use the DQ/DQS relationships to distinguish between Read / Write operations on the bus. Teledyne LeCroy's Kibra analyzer helps address this test challenge using dedicated, low latency SMA trigger-out to a scope for Read and Write operations (WE).
Demand from real time system developers will continue to push the evolution of memory to meet the need for improved performance, density and power efficiency.
Like all PC technologies, memory performance and density continue to evolve to meet the demands of faster CPUs. DDR2 was designed to deliver higher overall throughput, the main difference between DDR and DDR2 DRAM is that for DDR2 the memory cells are clocked at 1 quarter the rate of the bus. DDR2 RAM's bus frequency is boosted by electrical interface improvements, on-die termination, pre-fetch buffers and off-chip drivers. DDR2 RAM memory also uses a new form factor, a 240 pin DIMM (Dual Inline Memory Module) that is not compatible with the DDR1 standard.
| DDR2 | DDR3 | |
| Rated Speed | 400-800 Mbps | 800-1600 Mbps |
| Vdd/Vddq | 1.8V +/- 0.1V | 1.5V +/- 0.075V |
| Internal Banks | 4 | 8 |
| Termination | Limited | All DQ signals |
| Topology | Conventional T | Fly-by |
| Driver Control | OCD Calibration | Self Calibration with ZQ |
| Thermal Sensor | No | Yes (Optional) |
The newest DDR memory interface technology, DDR3, offers significant advantages over previous DDR generations. DDR3 supports data rates up to 1600 Mbps per pin with an operating voltage of 1.5 volts, a 17% reduction from the previous generation of DDR2, which operates at 1.8 volts. DDR3's built-in power conservation features, like partial refresh are desirable for mobile applications where battery power will no longer be needed just to refresh a portion of the DRAM not in active use. DDR3 also has a specification for an optional thermal sensor that allow mobile engineers to save further power by providing minimum refresh cycles.
Since DDR3 is designed to run at higher memory speeds the signal integrity of the memory module is now more important. DDR3 uses "fly-by" routing instead of the "T branches" seen on DDR2 modules. This means the address and control lines are a single path chaining from one DRAM to another, where DDR2 uses a T topology that branches on DDR2 modules. "Fly-by" takes away the mechanical line balancing and uses automatic signal time delay generated by the controller fixed at the memory system training. Each DDR3 DRAM chip has an automatic leveling circuit for calibration and to memorize the calibration data. DDR3 also uses more internal banks - 8 instead of the 4 used by DDR2 - to further speed up the system. More internal banks allow advance prefetch to reduce access latency.
All DDR memory access are burst oriented where an access starts at a selected location and continues for the burst amount. As an added complexity, Intel memory design uses interleaved burst type; with most other controllers using sequential burst type. The ability to distinguish between interleaved and sequential bursts during testing is a critical distinction when triggering on timing violations. Other complexities introduced with DDR3 include signal integrity testing on the Data lines. Because DQ/DQS are bidirectional, developers must use the DQ/DQS relationships to distinguish between Read / Write operations on the bus. Teledyne LeCroy's Kibra analyzer helps address this test challenge using dedicated, low latency SMA trigger-out to a scope for Read and Write operations (WE).
Demand from real time system developers will continue to push the evolution of memory to meet the need for improved performance, density and power efficiency.
Kibra 480 DDR3 SO-RDIMM (with ECC) Interposer Dx series
The Kibra 480 DDR3 Dx series interposers for SO-R DIMM with ECC module types incorporate proprietary circuitry to support higher speed DDR3 memory. The SO-RDIMM slot interposers are available for the Kibra 480 system only and are capable of monitoring two slots of DDR3 Registered SO-DIMMs operating to 2133 MT/s.
- Compatible with all standard 204-pin DDR3 SO-RDIMMs at speeds up to 2133 MT/s
- Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
- Integrated cable (18" length) between analyzer and system-under-test
- DDR3 Interposer probes operate non-intrusively and introduce less than 95 ps of latency to the DDR3 signal
- Model numbers: Slot 1 - DDR-AC20-D02-X; Slot 2 - DDR-AC21-D02-X
Kibra 480 DDR3 SO-UDIMM (with ECC) Interposer Dx series
The Kibra 480 DDR3 Dx series interposers incorporate proprietary circuitry to support higher speed DDR3 memory. The SO-UDIMM (ECC) slot interposers are available for the Kibra 480 system only and are capable of monitoring two slots of DDR3 SO-UDIMM (ECC) operating to 2133 MT/s.
- Compatible with all standard 204-pin DDR3 SO-UDIMMs with ECC at speeds up to 2133 MT/s
- Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
- Integrated cable (18" length) between analyzer and system-under-test
- DDR3 Interposer probes operate non-intrusively and introduce less than 95 ps of latency to the DDR3 signal
- Model numbers: Slot 1 - DDR-AC18-D02-X; Slot 2 - DDR-AC19-D02-X
Kibra 480 DDR3 SO-UDIMM (non-ECC) Interposer Dx series
The Kibra 480 DDR3 Dx series interposers incorporate proprietary circuitry to support higher speed DDR3 memory. The SO-UDIMM (non-ECC) slot interposers are available for the Kibra 480 system only and are capable of monitoring two slots of DDR3 SO-UDIMM (non-ECC) operating to 2133 MT/s.
- Compatible with all standard 204-pin DDR3 SO-UDIMMs at speeds up to 2133 MT/s
- Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
- Integrated cable (18" length) between analyzer and system-under-test
- DDR3 Interposer probes operate non-intrusively and introduce less than 95 ps of latency to the DDR3 signal
- Model numbers: Slot 1 - DDR-AC16-D01-X; Slot 2 - DDR-AC17-D01-X
Kibra 480 DDR4 SO-DIMM Interposer Mx series
The Mx series probes for DDR4 SO-DIMM are designed for the Kibra 480 system only and incorporate proprietary circuitry to support higher speed DDR4 memory. These DIMM slot interposers are capable of monitoring two slots of DDR4 SO-DIMMs operating to 2400 MT/s.
- The Mx Series DDR4 SO-DIMM Interposer supports both ECC and non-ECC variants
- Compatible with all 256 pin DDR4 SO-DIMM at speeds up to 2400 MT/s
- Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
- Integrated cable (18" length) between analyzer and system-under-test
- Model numbers: Slot 1 - DDR-AC14-D02-X; Slot 2 - DDR-AC15-D02-X
Kibra 480 DDR3 DIMM Interposer Dx series
The Kibra 480 DDR3 Dx series interposers incorporate proprietary circuitry to support higher speed DDR3 memory. These DIMM slot interposers are available for the Kibra 480 system only and are capable of monitoring two slots of DDR3 DIMMs operating to 2133 MT/s.
- Compatible with all standard 240-pin DDR3 UDIMM's, RDIMM's, LRDIMM's at speeds up to 2133 MT/s
- Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
- Integrated cable (18" length) between analyzer and system-under-test
- DDR3 Interposer probes operate non-intrusively and introduce less than ~90 ps of latency to the DDR3 signal
- Model numbers: Slot 1 - DDR-AC10-D02-X; Slot 2 - DDR-AC11-D02-X
Kibra 480 DDR4 DIMM 284-pin Interposer Mx Series
The Kibra 480 284-pin DDR4 Mx series probes incorporate proprietary circuitry to support higher speed DDR4 memory. These DIMM slot interposers are capable of monitoring two slots of DDR4 DIMMs operating to 2400 MT/s.
- Compatible with all standard 284-pin DDR4 UDIMM's, RDIMM's, LRDIMM's at speeds up to 2400 MT/s
- Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
- Integrated cable (18" length) between analyzer and system-under-test
- DDR4 Interposer probes operate non-intrusively and introduce less than ~90 ps of latency to the DDR4 signal
- Model numbers: Slot 1 - DDR-AC08-D02-X; Slot 2 - DDR-AC09-D02-X
Kibra 480 DDR4 DIMM 288-pin Interposers Mx Series
The Kibra 480 288-pin DDR4 Mx series probes incorporate proprietary circuitry to support higher speed DDR4 memory. These DIMM slot interposers are capable of monitoring two slots of DDR4 DIMMs operating to 2400 MT/s.
- Compatible with the new 288-pin DDR4 UDIMM's, RDIMM’s, LRDIMM’s connector at speeds up to 2400 MT/s.
- Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
- Integrated cable (18” length) between analyzer and system-under-test
- DDR4 Interposer probes operate non-intrusively and introduce less than ~90 ps of latency to the DDR4 signal
- Model numbers: Slot 1 - DDR-AC22-D02-X; Slot 2 - DDR-AC23-D02-X
